The present invention relates in general to waveform sampling circuits and in particular to a bridge-type sample and hold circuit for high frequency operation.
Sample and hold circuits typically charge a capacitor to the current magnitude of a sampled voltage waveform signal during a sampling interval and then disconnect the capacitor from the signal during a holding interval. The voltage stored on the capacitor is then typically converted by an analog-to digital converter to a corresponding digital value which may be stored by a memory device such as a random access memory. A set of such stored digital values obtained at various points during a sampled waveform cycle comprises a digital approximation of the analog waveform and has many uses.
One commonly used sample and hold circuit is the sampling bridge circuit of FIG. 1. The circuit includes a Schottky diode bridge comprising two diodes CR1 and CR2 having anodes connected to node A, and two other diodes CR3 and CR4 having cathodes connected to node B. The cathode of diode CR1 is connected to the anode of diode CR3 at node C and the cathode of diode CR2 is connected to the anode of diode CR4 at node D. A voltage waveform to be sampled, Vi, is applied as an input to the diode bridge at node C while the sampled output voltage Vo appears at node D. The output voltage Vo charges holding capacitor Chold. A first strobe current source IS1 is applied to node A while a second strobe current source IS2 is applied to node B. A clamping diode D1 connects node A to ground with the cathode of diode D1 being applied to node A, while another clamping diode D2 connects node B to ground with the cathode of diode D2 being grounded.
During a holding interval, when the input waveform Vi is not being sampled, the strobe current sources IS1 and IS2 are directed such that diodes CR1-CR4 are reverse biased, thereby disassociating Vo from Vi. Diodes D1 and D2 are both forward biased and clamp the strobe signal voltages VS1 and VS2 at nodes A and B to one diode forward bias voltage drop below and above ground respectively. To initiate a sampling interval, the directions of IS1 and IS2 are reversed such that diodes CR1-CR4 are forward biased, coupling Vo to Vi and allowing Chold to charge to the current magnitude of Vi. When strobe currents IS1 and IS2 are reversed once again, the reverse biased bridge diodes CR1-CR4 uncouple Vo from Vi such that the value Vi at the moment of strobe reversal remains on Chold.
Diodes CR1-CR4 all have inherent parallel capacitance. When the output signal Vo at node D is not centered between the voltages VS1 and VS2 at nodes A and B (i.e. when Vi is not at ground) at the moment a holding interval begins, the strobe reversal pumps unequal amounts of charging current through diodes CR2 and CR4. Charge is removed or added to Chold to make up the difference, causing the sampled voltage on Chold to decrease or increase just after the sampling strobe ends and introducing an error into the sampled voltage. Because the diode capacitance as a function of voltage is non-linear, this "strobe feedthrough" error is nonlinear with respect to the deviation of magniture of Vi at the moment of sampling from ground. As this strobe feedthrough effect is inversely proportional to Chold, it precludes reducing Chold to increase bandwidth or to shorten acquisition time, thus limiting the strobing frequency. FIG. 2 is a signal diagram depicting the behavior of Vi, VS1, VS2 and Vo of FIG. 1 during sample and hold intervals and illustrates the strobe feedthrough error in Vo.
The inherent capacitances of CR1-CR4 also allow some coupling of Vi to Vo during a holding interval, causing changes in the voltage held by Chold as Vi deviates from the last sampled value. This "blowby" error is more pronounced as the Vi signal frequency increases. Thus the input signal Vi bandwidth of the circuit of FIG. 1 and the strobe signal switching frequency are limited by the capacitance associated with the bridge diodes.
A prior art improvement to the bridge sample and hold circuit is shown in FIG. 3. In this circuit, strobe feedthrough is reduced by coupling clamping diodes D1 and D2 to Vo through a buffer B1. Circuit output Vout is taken at the output of buffer B1. This arrangement ensures that Vo is centered between VS1 and VS2 at the moment of strobe reversal so that no change in the charge on Chold is necessary to balance current flow in D1 and D2 immediately after strobe reversal. However, while the circuit of FIG. 3 reduces strobe feedthrough in comparison to the circuit of FIG. 1, it increases blowby error since the inherent capacitances associated with D1 and D2 in FIG. 2 now increase the coupling of Vi to Vout during a holding interval. Also, delay in buffer B1 causes this feedthrough compensation to be imperfect, with error increasing as input frequency increases.
What is needed and would be useful is a sample and hold circuit wherein strobe feedthrough is minimized without increasing signal blowby.